CSCI 2021 Lab 0x9: Extending Y86-64

The Y86-64 instruction set provides the command IOPQ for doing arithmetic on two numbers. Each operrand must be loaded into a register beforehand. While this is a simple approach, it is inefficient when one of your operands is a constant value since you must load it ahead of time in another register (registers are a scarce resource!). In this lab you will extend Y86-64 by adding an instruction that allows arithmetic between one immediate value and one register called IADDQ.

IADDQ has the effect of adding a constant to a register, with the new value stored in the same regsiter.

iaddq V, rB rB <- rB + V

The instruction enncoding of IADDQ, is as follows:

byte 0 bits [0:3]: C Instruction code 0xC byte 0 bits [3:7]: 0 Unused byte 1 bits [0:3]: F Source 1 set to unused value 0xF byte 1 bits [3:7]: rB Source 2 set to register rB bytes 2-9: V Constant value to add to rB

Getting Started

Extract the lab files with this commands:

unix> cp /web/classes/Fall-2018/csci2021-010/labs/0x9/lab0x9.tar.gz .

unix> tar -xvf lab0x9.tar.gz

We will be working in directory lab0x9/seq. Now is a good time to review the HCL language. Begin by studying seq-full.hcl. See how each stage in the processor (Fetch, Decode, etc.), control signals, and the Program Counter are all described in HCL. This is a programmatic representation of the logic of SEQ (a sequential processor).

Lets look at IOPQ as an example to help us get started.

• Declaration

  Each instruction is declared with a string name. IOPQ's declaration is

  wordsig IOPQ 'I_ALU'

  The declaration of IADDQ is done for you.

• Fetch

  Recall that HCL statement's like

  var in {list}

  evaluate to true if var is found in the list and false if not. In the Fetch section we see this in action where IOPQ is listed under the instr_valid control signal. Add IADDQ to this list since you want it to be read as a valid instruction.

  Look at the other control signals generated during Fetch. Which of these will IADDQ need?

• Decode

  Now recall HCL switch statements

  [ boolExpr1: value1; boolExpr2: value2; ... boolExprN: valueN; ]

  return the value corresponding to the boolean expression that evaluates as true. The list-containment expression from Fetch is used as a boolean expression.

  In IOPQ, registers rA and rB are identified as the sources for the ALU. IADDQ also has a register input to the ALU, but how will you encode the logic for the constant value?

• Execute, Memory Stage, PCU Update

  Once you've identified IADDQ's input sources in Decode, you are ready to plug them into the ALU. We've covered all the HCL syntax you need to continue. Use IADDQ's similarity to IOPQ to decide how to finish the Execute and Memory Stages.

Building and Testing Your Solution

Once you have finished modifying the seq-full.hcl file, you will need to build a new instance of the SEQ simulator (ssim) based on your HCL file, and then test it:

• Building a new simulator. You can use make to build a new SEQ simulator:

  unix> make

  This builds a version of ssim that uses the control logic you specified in seq-full.hcl.

• Testing your solution on a simple Y86-64 program. For your initial testing, we recommend running simple programs such as asumi.yo (testing iaddq) in TTY mode, comparing the results against the ISA simulation:

  unix> ./ssim -t ../y86-code/asumi.yo

  You will know your implementation passed this test when the register rax contains the value 0xabcdabcdabcd and the output message reads "ISA Check Succeeds". If the ISA test fails, then you can try debugging your implementation by single stepping the simulator in GUI mode:

  unix> ./ssim -g ../y86-code/asumi.yo

• Retesting your solution using the benchmark programs. Once your simulator is able to correctly execute small programs, then you can automatically test it on the Y86-64 benchmark programs in ../y86-code:

  unix> (cd ../y86-code; make testssim)

  This will run ssim on the benchmark programs and check for correctness by comparing the resulting processor state with the state from a high-level ISA simulation. Note that none of these programs test the added instructions. You are simply making sure that your solution did not inject errors for the original instructions. See file ../y86-code/README file for more details.

• Performing regression tests. Once you can execute the benchmark programs correctly, then you should run the extensive set of regression tests in ../ptest. To test everything except iaddq:

  unix> (cd ../ptest; make SIM=../seq/ssim)

  To test your implementation of iaddq:

  unix> (cd ../ptest; make SIM=../seq/ssim TFLAGS=-i)

For more information on the SEQ simulator refer to the handout CS:APP3e Guide to Y86-64 Processor Simulators(simguide.pdf).